In a digital signal that is output from a transmitter, when a clock is not transmitted simultaneously, it is necessary for the side of a receiver thereof to restore a clock and data. A clock data restoration device that performs such restoration is disclosed in, for example, non-patent literature 1. The clock data restoration device disclosed in this document includes a sampler portion, a digital phase comparison portion, a charge pump, a loop filter and a voltage control oscillator. Depending on the structure of the phase comparator used, the clock data restoration device has a bang-bang type PLL (phase lock loop) structure or an Alexander type PLL structure.
The clock data restoration device operates as follows. In the sampler portion, the value of an input digital signal is sampled, held and output with timing indicated by the clock output from the voltage control oscillator. In the phase comparison portion, based on the value output from the sampler portion, the phase of the clock output from the voltage control oscillator and the phase of the input digital signal are compared, and a phase difference signal indicating the phase difference between them is output. The charge pump that inputs the phase difference signal outputs a charge and discharge current corresponding to the phase difference indicated by the phase difference signal.
This charge and discharge current is input to the loop filter. A control voltage value output from the loop filter is input to the voltage control oscillator. Then, a clock having a frequency corresponding to the control voltage value is output from the voltage control oscillator, and this clock is fed to the sampler portion. The clock that has been restored from the input digital signal as described above is output from the voltage control oscillator; the data restored from the input digital signal is output from the sampler portion.